1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a display device including a driving circuit polycrystalline silicon driving circuit and a method of fabricating the same.
2. Discussion of the Related Art
As the information age progresses, flat panel display (FPD) devices having high portability and low power consumption is becoming the trend of recent research and development. Among various types of FPD devices, liquid crystal display (LCD) devices are commonly used as monitors for notebook and desktop computers because of their ability to display high-resolution images, wide ranges of different colors, and moving images.
In general, the LCD device includes a color filter substrate and an array substrate separated from each other by having a liquid crystal layer interposed there between, wherein the color filter substrate and the array substrate include a common electrode and a pixel electrode, respectively. When a voltage is supplied to the common electrode and the pixel electrode, an electric field is generated that changes the orientation of liquid crystal molecules of the liquid crystal layer due to optical anisotropy within the liquid crystal layer. Consequently, light transmittance characteristics of the liquid crystal layer is modulated and images are displayed by the LCD device.
Active matrix type display devices are commonly used because of their superiority in displaying moving images. Active matrix-type display devices include pixel regions disposed in a matrix form where a thin film transistor (TFT) is formed in the pixel region as a switching element. While forming the TFT, hydrogenated amorphous silicon (a-Si:H) is selected to be deposited over a large area of substrate. Hydrogenated amorphous silicon yields higher productivity while easily fabricated on the large area of the substrate. In addition, the hydrogenated amorphous silicon (a-Si:H) is deposited at a temperature less than about 350° C., a glass substrate of low cost can be used. Accordingly, the hydrogenated amorphous silicon is used mainly in the TFT, which is referred to as an amorphous silicon thin film transistor (a-Si TFT).
However, since the hydrogenated amorphous silicon has a disordered atomic arrangement, weak silicon-silicon (Si—Si) bonds and dangling bonds exist in the hydrogenated amorphous silicon. These types of bonds become metastable when light or an electric field is applied to the hydrogenated amorphous silicon. As a result, this metastability makes the TFT unstable. Electrical characteristics of the hydrogenated amorphous silicon are especially degraded due to light irradiation. Furthermore, a TFT using the hydrogenated amorphous silicon is difficult to be implemented in a driving circuit due to degraded electric characteristics such as a low field effect mobility between about 0.1 cm2/Vsec to about 1.0 cm2/Vsec, and poor reliability.
In the related art TFT, the substrate including the a-Si TFT is connected to a printed circuit board (PCB) using a tape carrier package (TCP) that has a driving integrated circuit (IC). The driving IC and its packaging increase the LCD device production cost. Additionally, as the resolution of a liquid crystal display panel for an LCD device increases, a pad pitch between gate pads or between data pads of the a-Si TFT substrate becomes smaller. Thus, bonding of the TCP and the a-Si TFT substrate becomes harder.
To solve these problems, a polycrystalline silicon thin film transistor (p-Si TFT) is suggested. Due to a higher field effect mobility of a p-Si TFT as compared to an a-Si TFT, fabrication of a driving circuit and a switching element can be achieved simultaneously. Accordingly, the production cost is reduced and the TCP is removed. Moreover, p-Si TFT can be used as a switching element of a high-resolution panel to benefit from the high field effect mobility of the polycrystalline silicon. Furthermore, a p-Si TFT has a lower photo current than an a-Si TFT, thereby preventing the display device from the substantial degradation of display quality due to the exposure to light.
FIG. 1 is a schematic view showing a liquid crystal display device according to the related art where a switching element and a driving circuit are formed on a single substrate. In FIG. 1, a driving circuit portion 5 and a display area 3 are defined on a single substrate 1. The display area 3 is disposed at a central portion of the substrate 1, while the driving area 5 is disposed at left and top portions of the display area 3. The driving circuit portion 5 includes a gate driving circuit 5a and a data driving circuit 5b. The display area 3 includes a plurality of gate lines 7 connected to the gate driving circuit 5a and a plurality of data lines 9 connected to the data driving circuit 5b. The gate line 7 and the data line 9 intersect each other to define a pixel region “P”. A pixel electrode 10 is formed in the pixel region “P.” A thin film transistor (TFT) “T” formed as a switching element is connected to the pixel electrode 10. The gate driving circuit 5a supplies a scan signal to the TFT “T” from the gate line 7 and the data driving circuit 5b supplies a data signal to the pixel electrode 10 from the data line 9.
The gate driving circuit 5a and the data driving circuit 5b are connected to an input terminal 12 to receive external signals. Accordingly, the gate driving circuit 5a and the data driving circuit 5b process the externals signals from the input terminal 12 to generate the scan signal and the data signal. To generate the scan signal and the data signal, the gate driving circuit 5a and the data driving circuit 5b include a plurality of TFTs forming complementary metal-oxide-semiconductor (CMOS) logic. For example, an inverter including negative (n)-type and positive (p)-type TFTs may be formed in the gate driving circuit 5a and the data driving circuit 5b. 
FIGS. 2A to 2F are schematic cross-sectional views showing a process of fabricating a thin film transistor in a display area of a liquid crystal display device according to the related art. FIGS. 3A to 3F are schematic cross-sectional views showing a process of fabricating n-type and a p-type thin film transistors in a driving area of a liquid crystal display device according to the related art.
In FIGS. 2A and 3A, a buffer layer 25 is formed on a substrate 20 and an amorphous silicon layer is formed on the buffer layer 25. The amorphous silicon layer is crystallized to a polycrystalline silicon layer by a laser annealing method. The amorphous silicon layer may be dehydrogenated before crystallizing to a polycrystalline silicon layer. The polycrystalline silicon layer is patterned through a first mask process to form a first semiconductor layer 30 in a pixel TFT portion “I,” a second semiconductor layers 35 in an n-type driving TFT portion “II” and a third semiconductor layer 40 in a p-type driving TFT portion “III.”
In FIGS. 2B and 3B, a gate insulating layer 45 of silicon oxide (SiO2) is formed on the semiconductor layers 30, 35 and 40. After depositing a metallic material on the gate insulating layer 45, first, second and third gate electrodes 50, 55 and 60 are formed on the gate insulating layer 45 through a second mask process. Then, the semiconductor layers 30, 35 and 40 are doped with low concentration n-type (n−) impurities using the gate electrodes 50, 55 and 60 as doping masks. Accordingly, a portion of the first semiconductor layer 30 directly underneath the first gate electrode 50 is not doped with n− impurities, while the other portion of the first semiconductor layer 30 is doped with n− impurities. Similarly, the second and third semiconductor layers 35 and 40 are partially doped with n− impurities. As a result, the semiconductor layers 30, 35 and 40 are divided into undoped regions 30a, 35a and 40a and n− doped regions 30b, 35b and 40b. The undoped regions 30a, 35a and 40a are used as an active region of a TFT.
In FIGS. 2C and 3C, first, second and third n+ photoresist (PR) patterns 61, 62 and 63 are formed through a third mask process. The first and second n+ PR patterns 61 and 62 cover the first and second gate electrodes 50 and 55, respectively. In addition, the first n+ PR pattern 61 covers a predetermined portion of the first semiconductor layer 30 adjacent to the first gate electrode 50 and the second n+ PR pattern 62 covers a predetermined portion of the second semiconductor layer 35 adjacent to the second gate electrode 55. The third n+ PR pattern 63 completely covers the third semiconductor layer 40 including the third gate electrode 60. Next, the first, second and third semiconductor layers 30, 35 and 40 are doped with high concentration n-type impurities (n+) using the first, second and third n+ PR patterns 61, 62 and 63 as doping masks. Accordingly, the predetermined portions of the first and second semiconductor layers 30 and 35 are not doped with n+ impurities, while the exposed portions of the first and second semiconductor layers 30 and 35 are doped with n+ impurities. In addition, the third semiconductor layer 40 is not doped with n+ impurities. As a result, the exposed portions of the first and second semiconductor layers 30 and 35 become n+ doped regions 30c and 35c, which are used as an ohmic contact regions of n-type, and the predetermined portions of the first and second semiconductor layers 30 and 35 that remain n− doped regions 30b and 35b are used as a lightly doped drain (LDD) region. Therefore, the active regions 30a and 35a, the LDD regions 30b and 35b, and the n-type ohmic contact regions 30c and 35c are defined by doping with n− impurities and n+ impurities. After doping with n+ impurities, the first, second and third n+ PR patterns 61, 62 and 63 are removed.
In FIGS. 2D and 3D, the first and second p+ PR patterns 65 and 66 are formed through a fourth mask process. The first and second p+ PR patterns 65 and 66 completely cover the first and second semiconductor layers 30 and 35, respectively. The third semiconductor layer 40 is exposed, since no p+ PR pattern is provided in the portion “III”. Next, the semiconductor layers 30, 35 and 40 are doped with high concentration p-type (p+) impurities using the first and second p+ PR patterns 65 and 66 and the third gate electrode 60 as doping masks. Accordingly, the first and second semiconductor layers 30 and 35 are not doped with p+ impurities. In addition, a portion of the third semiconductor layer 40 directly underneath the third gate electrode 60 is not doped with p+ impurities, while the other portion of the third semiconductor layer 40 is doped with p+ impurities. Since the p-type impurities has a concentration higher than the n-type impurities in the exposed portion of third semiconductor layer 40, the p-type impurities compensate the n-type impurities. Accordingly, the exposed portion of the third semiconductor layer 40 becomes p+ doped region 40b which is used as an ohmic contact region of p-type. Therefore, the active regions 40a and the p-type ohmic contact region 40b are defined by doping with p+ impurities. After doping with p+ impurities, the first and second p+ PR patterns 65 and 66 are removed.
In FIGS. 2E and 3E, an interlayer insulating layer 70 of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO2) is formed on the gate electrodes 50, 55 and 60 through a fifth mask process. The interlayer insulating layer 70 has semiconductor contact holes 73a, 73b, 75a, 75b, 77a and 77b defined through the gate insulating layer 45 to expose the ohmic contact regions 30c, 35c and 40c. First source and drain electrodes 80a and 80b, second source and drain electrodes 83a and 83b, and third source and drain electrodes 87a and 87b are formed on the interlayer insulating layer 70 through a sixth mask process. The source and drain electrodes 80a, 80b, 83a, 83b, 87a and 87b have a double layer structure formed of molybdenum (Mo) and aluminum-neodymium (AlNd), and are connected to the ohmic contact regions 30c, 35c and 40c within the semiconductor contact holes 73a, 73b, 75a, 75b, 77a and 77b. 
In FIGS. 2F and 3F, a passivation layer 90 of silicon nitride (SiNx) is formed on the source and drain electrodes 80a, 80b, 83a, 83b, 87a and 87b through a seventh mask process. The passivation layer 90 may be hydrogenated and has a drain contact hole 95 exposing the first drain electrode 80b. Next, a pixel electrode 97 of indium-tin-oxide (ITO) is formed on the passivation layer 90 through an eighth mask process. The pixel electrode 97 is connected to the first drain electrode 80b within the drain contact hole 95.
As mentioned above, the array substrate for an LCD device according to the related art is fabricated through a eight-mask process. Since the related art mask process includes steps of coating PR, exposing PR, and developing PR, increase in production cost and fabrication time as well as a reduced production yield results from an increased number of masks. In addition, reliability of a thin film transistor is reduced accordingly.